YosysHQ / picorv32
PicoRV32 - A Size-Optimized RISC-V CPU
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PicoRV32 - A Size-Optimized RISC-V CPU
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
The Ultra-Low Power RISC-V Core
FPGA cores compatible with multiple arcade game machines and KiCAD schematics of arcade games. Working on MiSTer FPGA/Analogue Pocket
SERV - The SErial RISC-V CPU
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
The USRP™ Hardware Driver Repository
SystemVerilog support for Yosys
Verilog Ethernet components for FPGA implementation
Verilog PCI express components
HDL libraries and projects